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Preliminary Data Sheet
I DD Specifications and Conditions
(0°C ≤ T CASE ≤ + 85°C; V DDQ = +1.5V ± 0.075V, V DD = +1.5V ± 0.075V)
Rev.0.9
20.09.2011
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
Symbol
I DD0
10600-999
495
max.
8500-777
495
Unit
mA
t RC = t RC (I DD ); t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
I DD1
585
585
mA
I OUT = 0mA; BL = 4, CL = CL (I DD ), AL = 0;
t CK = t CK (I DD ), t RC = t RC (I DD ), t RAS = t RAS MIN (I DD ),
t RCD = t RCD (I DD ); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as I DD4W
PRECHARGE POWER-DOWN
CURRENT:
Fast Exit
I DD2P
270
270
mA
All device banks idle; Power-down mode;
t CK = t CK (I DD ); CKE is LOW; All Control and Slow Exit
Address bus inputs are not changing; DQ’s
are floating at V REF
270
270
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
I DD2Q
360
360
mA
t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at V REF
PRECHARGE STANDBY CURRENT:
All device banks idle;
I DD2N
450
360
mA
t CK = t CK (I DD ); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
I DD3P
360
360
mA
All device banks open; t CK = t CK (I DD ); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at V REF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; t CK = t CK (I DD ),
I DD3N
540
540
mA
t RAS = t RAS MAX (I DD ), t RP = t RP (I DD );
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
I DD4R
900
765
mA
module rank active; I OUT = 0mA; BL = 4, CL = CL (I DD ),
AL = 0; t CK = t CK (I DD ), t RAS = t RAS MAX (I DD ), t RP = t RP
(I DD ); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 7
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